How to use Xilinx 7-series MIG in your Design?

After making sure that PCB hardware has no problem by using MG example design, the next  step is to instance MIG in your design.
In this post, a MIG had been generated and its name is mig_7series_0.

All steps to instance MIG are shown below.

1. In Vivado’s Source window, click tab “IP Source”. Find file mig_7series_0.veo under mig_7series_0/Instantiation Template.

The mig_7series_0.veo tells you the most top module name and IO pin of MIG.


2. Instance MIG into your design. The MIG’s example design is the best example you can refer.

The MIG’s example design is in fold <vivado project>/<vivado project>.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/rtl/ and example_top.v is the target.

3.1 If you use AXI bus for MIG, connect MIG to an AXI master.

If you have two or more AXI masters that will control IP MIG, you can instance an IP called “AXI interconnect” between all AXI masters and MIG.

Below picture shows you an example:

3.2 If you don’t use AXI bus for MIG, please see page 164 to 172 of UG586 to know how to control MIG’s read/write path.

If you have to modules that will control MIG, you have to create an IP arbitrator by yourself.





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