Tutorial:Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC

Chapter 9: Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC

In chapter 2, we create a block design that includes PS of MPSOC and AXI GPIO/Timer in PL. In this block design, AXI GPIO and AXI Timer can’t issue interrupt events to PS because the interrupt signals of AXI GPIO and AXI Timer are floating. Now we want AXI timer can send an interrupt signal to PS in this tutorial. An example C code to handle this interrupt is also listed in this tutorial.

1. Open the block design created in chapter 2 then connects AXI timer’s interrupt port to MPSOC’s pl_ps_irq. The result should be:
Sending_an_Interrupt_from_PL_to_PS_for_Xilinx_Zynq_Ultrascale+_MPSOC1.png

Read moreTutorial:Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC

A Tutorial for Using Xilinx Zynq Ultrascale+ MPSOC

This post provides a tutorial to use the Xilinx Vivado Design Suite for Xilinx Zynq UltraScale+ MPSoC device. Xilinx ZCU102 is the target board for this tutorial.

The Zynq UltraScale+ MPSOC comes with a versatile Processing System (PS) integrated with a highly flexible and high-performance Programmable Logic (PL) section, all on a single System on Chip (SoC). Here is the block diagram:

Read moreA Tutorial for Using Xilinx Zynq Ultrascale+ MPSOC

Tutorial:Creating a New Vivado Project for Xilinx Zynq Ultrascale+ MPSOC

Chapter 1: Creating a New Vivado Project for Xilinx Zynq Ultrascale+ MPSOC

The Xilinx Zynq Ultrascale+ MPSoC family integrates a feature-rich 64-bit ARM Cortex-A53(quad-core or dual-core)  and dual-core ARM Cortex-R5 based processing system (PS) and Xilinx UltraScale+ architecture programmable logic(PL) in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces.

Xilinx Vivado is a key development tool for using Xilinx Zynq Ultrascale+ MPSoC. It is used for configuring processing system(PS) and integrating/implementing the logic function in the programmable logic(PL). It is also responsible for connecting PS and PL. In this serial of tutorials, Vivado‘s IP integrator is used for implementing logic circuit inside the programmable logic. And if all IPs are available on the Vivado‘s IP integrator, you don’t need to code any Verilog or VHDL. However, creating a Vivado project is the first step. Let’s go.

Read moreTutorial:Creating a New Vivado Project for Xilinx Zynq Ultrascale+ MPSOC

Tutorial: Using XSDK Debug Function for Xilinx Zynq Ultrascale+ MPSOC

Chapter 8: Using XSDK Debug Function for Xilinx Zynq Ultrascale+ MPSOC

  This article is a series of articles using Xilinx Ultrascale+ MPSOC. In chapter 7, a project marquee in C is created and compiled. Then target board goes into the debug mode by creating a debug configuration. This article shows you the layout and the key features of XSDK’s debug mode.

1 Below picture shows XSDK’s debug layout:
Window 1 shows the status of APUs and RPUs.
Window 3 shows program’s source code
In Windows 2, you can review the value of the variables in tab Variables, breakpoints in tab Breakpoints, the value of registers in tab Registers.
Using Xilinx XSDK Debug Function for Xilinx Zynq Ultrascale+ MSOC1.png

Icon Using Xilinx XSDK Debug Function for Xilinx Zynq Ultrascale+ MSOC2.png  (resume) lets CPU run the program freely
Icon Using Xilinx XSDK Debug Function for Xilinx Zynq Ultrascale+ MSOC3.png (Step Into) lets CPU execute each C statement step by step. It steps into the subroutine
Icon Using Xilinx XSDK Debug Function for Xilinx Zynq Ultrascale+ MSOC4.png (Step over) lets CPU execute each C statement step by step. It steps over the subroutine
Icon Using Xilinx XSDK Debug Function for Xilinx Zynq Ultrascale+ MSOC5.png (Step Return) lets CPU run remain codes of a subroutine and then returns to the subroutine which had been stepped into

Read moreTutorial: Using XSDK Debug Function for Xilinx Zynq Ultrascale+ MPSOC