SDSoC Error Message: ‘gnu/stubs-32.h’ file not found

When you got an error message like below in Xilinx SDSoC:

ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling ‘/ap/Xilinx/Vivado/2017.4/bin/vivado_hls /fold/aaa/Debug/_sds/vhls/to_hardware_run.tcl -l CONVOLUTION_LAYER_1_vivado_hls.log’
sds++ log file saved as /fold/aaa/Debug/_sds/reports/sds_image_convolution.log
ERROR: [SdsCompiler 83-5004] Build failed



After reviewing the log file, you can know SDSoC couldn’t find gnu/stubs-32.h. To fix this problem, you need to install glibc-devel.i686 for Centos 7 by using:

yum install glibc-devel.i686

How to Change Pin Assignment for Xilinx Memory Controller under Vivado

Xilinx DDR memory controller always has default pin assignments but they are not always friendly for PCB layout. For complying with DDR memory PCB layout constraints, pin swap is a good strategy. However, there are many pin assignment constraints to follow and it is not an easy job to understand them. Good news is Xilinx development tool Vivado can help you. By running DRC check with modified xdc file in “Open Synthesis Design”,  you can know all of DDR memory controller pins meet pin assignment constraints or not. The following picture shows all DDR pin assignment constraints are met:

Read moreHow to Change Pin Assignment for Xilinx Memory Controller under Vivado

Fix Xilinx Tools Can’t Connect to the Download Cable in Virtual Machine

Virtual Machine is a very useful tool to run a guest OS in a master OS. By using it, you can run Xilinx development tools such as Vivado, XSDK, SDAceel and SDSOC in a Linux OS to get better performance under the Windows OS. Most people already did it but having a problem when Xilinx development tools connect to a USB peripheral called download cable. The Xilinx Development tools may give you this error message:

Read moreFix Xilinx Tools Can’t Connect to the Download Cable in Virtual Machine

How to program or debug Xilinx FPGA remotely?

In most case, the Xilinx FPGA target board is connected to a local computer to download FPGA’s bitstream, use the chipscope and debug C/C++ program. However, sometimes the Xilinx FPGA target board needs to be connected to a faraway computer. Is it possible to connect to the Xilinx FPGA target board by a remote computer and do the jobs mentioned earlier successfully?

The answer is “Sure, you can easily connect to a Xilinx FPGA target board by using Xilinx development tools remotely”. The key program for this application is “hw_server”. Below picture shows an example.

A local computer runs windows 64-bit and its IP is 10.8.2.171. Xilinx FPGA target board is connected to it. Xilinx Vivado and XSDK are executed on the server. Each computer has different settings to remotely control a Xilinx FPGA target board:

Read moreHow to program or debug Xilinx FPGA remotely?

How to Adjust the Speed of JTAG Interface in Xilinx Vivado?

  Sometimes Vivado’s hardware manager can’t connect to target board mounted with Xilinx FPGA stably. Causing lots of functionality of Vivado Chipscope and FPGA/PROM programming issues. There are many root causes of this phenomenon. This post shows you a potential way to eliminate connection issue between Vivado Hardware Manager and target board.

1 Launch Xilinx Vivado design tool

 


Read moreHow to Adjust the Speed of JTAG Interface in Xilinx Vivado?

How to use Xilinx 7-series MIG in your Design?

After making sure that PCB hardware has no problem by using MG example design, the next  step is to instance MIG in your design.
In this post, a MIG had been generated and its name is mig_7series_0.

All steps to instance MIG are shown below.

1. In Vivado’s Source window, click tab “IP Source”. Find file mig_7series_0.veo under mig_7series_0/Instantiation Template.

Read moreHow to use Xilinx 7-series MIG in your Design?

Tutorial:Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC

Chapter 9: Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC

In chapter 2, we create a block design that includes PS of MPSOC and AXI GPIO/Timer in PL. In this block design, AXI GPIO and AXI Timer can’t issue interrupt events to PS because the interrupt signals of AXI GPIO and AXI Timer are floating. Now we want AXI timer can send an interrupt signal to PS in this tutorial. An example C code to handle this interrupt is also listed in this tutorial.

1. Open the block design created in chapter 2 then connects AXI timer’s interrupt port to MPSOC’s pl_ps_irq. The result should be:
Sending_an_Interrupt_from_PL_to_PS_for_Xilinx_Zynq_Ultrascale+_MPSOC1.png

Read moreTutorial:Sending an Interrupt from PL to PS for Xilinx Zynq Ultrascale+ MPSOC